Integrated circuit design involves assembling a model from a combination of circuits that perform desired functions. Generally, the combination of circuits is constructed from building blocks called cells. Each cell performs a specific function and has a defined set of inputs and outputs. The different cells are deployed as necessary in the model to meet differing needs. A selected mix of such cells from the library is arranged in the model depending upon the desired function of the integrated circuit.
The set of such cells available to an integrated circuit designer is stored in a library of cells. A cell library may comprise a hundreds or even thousands of cells corresponding to primitive function circuits, such as inverters, NAND gates, NOR gates, more complex Boolean function circuits and even sequential elements like latches and flip-flops. A cell may itself be defined in terms of a netlist that includes a cell model that specifies logical, electrical, and physical attributes and that may include one or more smaller circuits. Other cell attributes provide information concerning a variety of the cell's characteristics such as timing, area, power dissipation, testability and threshold voltage, for example.
A crucial factor in the performance of an integrated circuit is the cell to cell timing of clock and data signals. Complex circuits often include cells arranged in sequence with one or more cell outputs driving another cell's input. Integrated circuits are typically clock rate driven. Consequently, many such serial chains of cells must provide their outputs before the expiration of an interval of time. Proper circuit function depends upon meeting such timing restraints in virtually all of the integrated circuit. Accordingly, input and output signal timing requirements of the integrated circuit model are checked to verify that the model can be used to produce an integrated circuit that performs in a desired way over a range of operating conditions.
The library of cells can include a variety of cells that perform the same function. For example, a cell library may include multiple different cells that perform a two-input NAND logic function, but each such functionally equivalent cell may employ transistors having different threshold voltages. A cell with transistors that have a relatively lower threshold voltage will switch faster than a comparative cell with transistors that have a higher threshold voltage. Thus, it is common for circuit designers to select a cell with transistors that have a lower threshold voltage when the cell is in a critical timing path. However, cells that include transistors with a relatively lower threshold voltage consume much more power when the cell is not in use. The power consumed when a cell is not in use is often known as leakage power.
The inherent trade-off between power dissipation and switching speed when selecting between cells having different threshold voltages created a need for an analysis system and method that would seek a suitable balance between leakage power consumed and integrated circuit timing constraints. Leakage optimization techniques have been deployed within placement and routing tools for modeling an integrated circuit.
However, use of these optimization techniques in placement and routing tools has been problematic. For example, some placement and routing tools cannot optimize an integrated circuit design to provide less than a desired percentage of low threshold voltage cells. Still other placement and routing tools cannot define an integrated circuit design that would achieve a desired timing margin. For some of these situations, it was discovered that even when a desired timing margin is not achieved, the placement and routing tool does not apply a solution using all low voltage threshold cells on the path. In other situations, it was discovered that low voltage threshold cells are applied in non-critical timing paths even when these paths have sufficient timing margins.
Furthermore, poor correlation between estimated delays used in an initial timing analysis in placement and routing tools and delays in a more robust final timing analysis that uses parasitic resistances and capacitances extracted from actual metal routes and transistor placement results in at least two additional problems when placement and routing tools are used to optimize the usage of low voltage threshold cells in an integrated circuit design. When a leakage optimization is performed using the less accurate estimated delays, and the correlation between the estimated delays and the delays derived from parasitic values is poor, it is often the case that any timing margin in the preliminary routing has been removed as a result of the leakage optimization. Often, when the more accurate final timing analysis is performed, many paths will fail to meet the required timing for the circuit to function across a desired range of operating conditions. Any paths that fail to meet the desired timing margin have to be readdressed and corrected. In an effort to reduce or eliminate the number of timing failures identified in a final timing analysis of a circuit, integrated circuit designers are motivated to increase the cell-to-cell timing margins used by the placement and routing tool. While increasing the cell-to-cell timing margin may make it possible to meet all timing constraints in the final timing analysis, it is likely that a significant number of low threshold voltage cells have been unnecessarily introduced in the circuit design. Thus, adding to the leakage power that will be dissipated in the integrated circuits constructed using the design.